Understanding quasi-ballistic transport in nano-MOSFETs: part II-Technology scaling along the ITRS

The on-current and its ballistic limit for MOSFETs designed according to the 2003 International Technology Roadmap for Semiconductors down to the 45-nm node, are evaluated by using the full-band, self-consistent Monte Carlo simulator with quantum-mechanical corrections described in Part I. Our results show that quasi-ballistic transport increases for L/sub G/ below approximately 50 nm and contributes most part of the I/sub ON/ improvements related to scaling. Thanks to a lower vertical electric field, double-gate silicon-on-insulator MOSFETs with ultrathin body and low channel doping achieve performance closer to the ballistic limit than the bulk counterparts.