Short-channel MOSFET's in the punchthrough current mode

Results of two-dimensional device analysis are compared with experiment for 0.8-µm Si-gate ion-implanted MOS devices operated under conditions of punchthrough transport. Characterization of the punchthrough mode of device operation (a critical factor which limits the maximum drain voltage of submicron MOS VLSI devices) with experiment and simulation has shown that the observed power-law dependence of I
DS
versus
V_{DS} (V_{GS} = V_{SB} = 0)
is related to the drain-induced barrier-height lowering. Results of the simulation show the dependence of the punchthrough current upon the range and maximum doping level of the channel implantation. Increasing the substrate-bias or applying a negative-gate voltage is shown to increase the punchthrough voltage. This simulation, which combines results of the process-simulation program (SUPREM) and device-simulation program (CADDET), is shown to predict the behavior of this mode of operation where previous one-dimensional theory has failed.