I. Introduction
Smart-Power applications require medium to highvoltage (typically 16 to 100 V) field-effect transistors (FETS) integrable in low-voltage CMOS processes. Low process cost, high performance, and reliability of the devices are also required. Low process cost is generally achieved trying to nest high-voltage transistors in a standard CMOS process flow with the minimum number of additional dedicated process steps. High performance, within the target voltage capability, is often translated into low drain/source on-state resistance and area consumption. Long-term reliability, especially for automotive, video and telecom products, is often a blocking issue, and invariably pushes both process and device design in the opposite direction with respect to cost and performance. Schematic (not to scale) vertical section of the high-voltage nMOS transistor showing the geometrical parameters of the device.