I. Introduction
To REDUCE the resistance–capacitance (RC) delay and power consumption further, the low- dielectric films along with Cu wires have been pursued aggressively. In 90-nm node technology, SiOC (dielectric constant: ) films have been considered as the main interlevel dielectric (ILD) instead of the fluorosilicate glass [(FSG) ] films used in 130-nm node technology [1]. With the continuous decrease in feature size and the introduction of low- dielectrics, however, the process complexity due to the delicate low- film and its reliability issues have become more serious.