3-D device modeling for SRAM soft-error immunity and tolerance analysis

Soft-error tolerance of static random-access memory (SRAM) devices has been predicted by using three-dimensional (3-D) and time-dependent device simulation in conjunction with circuit simulation. An inverter model developed for 3-D device simulation is described, along with the analysis of the inverters device response as a function of time. The output thus obtained was applied as an input voltage source in circuit simulation of unit SRAM cell and the stability of this bistable circuit is studied on that basis. The effects on soft-error immunity of changes in alpha-particle injection conditions and in load resistance and capacitance are described. The validity of the presented model is examined through comparison of the bit-error-rate dependence on incident angle of alpha particles to that of measured rates. To simulate the angular dependence, we introduce statistical distribution models for alpha-particle energy, position of incidence on the device surface, and angle of incident. Results of device/circuit simulation carried out with many sets of energy, position, and angle are presented. Reasonable agreement between results of simulation and experimental data without the use of adjustment parameters is demonstrated. A map of soft-error tolerance on the CR plane with critical charge Q/sub c/ as a parameter is presented and its derivation explained. An analytic expression for the tolerance is clarified by proposing an equivalent circuit model for the simulation of alpha-particle injection at the output node in an inverter circuit. Inverter modeling is shown to be essential to obtaining SRAM soft-error tolerance to high degrees of accuracy.

I. Introduction

Static random-access memories (SRAMs) and dynamic RAMs (DRAMs) are essential elements of mostly data-processing equipment, including broad-band mobile phones, personal computers, work stations, etc. The integration scale of semiconductor memories has reached the order of mega-to gigabits. This increase in integration has been achieved by miniaturizing the device structures.