I. Introduction
The key issue in scaling of nanometer-regime CMOSFETs is how to improve device performance without any degradation. Low-energy ion implantation below 5 keV is currently used to form a shallow source/drain extension (SDE) junction. As a result, degradation of current drivability is induced. This is because of high SDE resistance due to reduction of the gate-to-SDE overlap [1], [2], and degradation of the carrier activation efficiency. To solve these problems, phosphorus diffusion from phosphosilicate glass [3] and rapid vapor-phase doping (RVD) [4] have been developed. However, a shallow junction formation using solid-phase diffusion results in complex fabrication process, because it is difficult to form the doping region selectively. Therefore, an advanced source/drain technology that meets the above requirements is needed. Furthermore, to fabricate even higher performance CMOSFETs, an unconventional device structure, which provides the outermost limits of silicon scaling, with small parasitic capacitance and high current drivability is required [5], [6].