1 Introduction
As static and dynamic variability effects increase with technology scaling, the timing margins that are added to compensate for worst case static and dynamic variability effects are also increasing [1]. Design-time techniques to address static variability based on clock skew adjustment [2], soft-edge flip-flops [3], and latches [4] have been proposed in the literature. Postmanufacturing techniques like speed-binning can also reduce the timing margins necessary to offset static variability sources like process variations by assigning a different voltage/frequency to each chip during manufacturing test. This is possible because static variability sources do not change with time and are also workload independent. However, dynamic variability is both time and workload dependent. As a result, there is significant interest in solutions that provide runtime resilience to timing errors, thereby recovering the timing margins necessary to offset dynamic variability effects.