1 Introduction
The ITRS roadmap predicts that complementary metal oxide semiconductor (CMOS) feature sizes will shrink from 32 nm to sub-17 nm within the next few years, thereby increasing the number of cores that can be integrated on a single chip [1]. Recent projections have shown that it will be possible to have as many as 256 cores on-chip by 2017 [2], [3]. As the design of the communication fabric has become more challenging, a growing number of multicore designs have adopted the network- on-chips (NoCs) design paradigm for enhancing scalability and improving reliability. While metallic interconnects can provide the required bandwidth due to shorter wires between cores as seen in NoCs, ensuring high-speed intercore communication within the allocated power budget in the face of technology scaling (and increased leakage currents) will become a major bottleneck for future multicore designs [4], [5]. Moreover, fundamental signaling limitations (reflections, crosstalk), electromagnetic interference (EMI), clock skew, and other problems associated with metallic interconnects will only exacerbate the power dissipation problem and thereby limit the performance of future multicores [5].