Generalization of an Enhanced ECC Methodology for Low Power PSRAM

Error control codes (ECCs) have been widely used to maintain the reliability of memories, but ordinary ECC codes are not suitable for memories with long codewords. For portable products, power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve these issues, we have proposed a parallel encoding and decoding ECC scheme to reduce refresh power for an industrial pseudo-SRAM (PSRAM) with long codewords. In this paper, we briefly review the scheme and propose a systematic way to generate the parity check matrix for the new ECC scheme. We also modify the parity correction mechanism to reduce the operating power of the scheme. As for the 70 ns access time of the 256-MB PSRAM with 64-bit codewords and 16-bit I/O, experimental results show that the new ECC scheme can be integrated with the READ/WRITE operations with about 0.2 percent circuit area overhead and less than 3.5 ns encoding/decoding time. The new ECC architecture provides a flexible solution for memories with different widths of ECC codewords and I/O ports, without the error masking effect or reduction in reliability.

1 Introduction

As we keep shrinking the feature size of transistors and increasing the degree of integration for integrated circuits, the capacity of semiconductor memories is getting bigger and their speed getting faster. The negative impact for larger and faster memories is that signal integrity becomes a more difficult yet important issue, so far as product quality and reliability is concerned. To enhance the signal integrity in memories, error control codes (ECCs) and error detection and correction (EDAC) schemes have been widely implemented to tolerate soft errors and enhance reliability of memory products. Extra bits containing parity check information have to be stored along with the data bits, so the hardware overhead includes the encoding/decoding circuit and the memory space for parity bits. As a matter of fact, ECC can protect the memory from attacks of both hard and soft errors. The modified Hamming code and Hsiao code [1], [2] are the most widely used single-error correctable and double-error detectable (SEC-DED) codes. For dealing with multiple errors, a code with more parity-bits is required, such as the BCH code [3], [4] that is a class of random error correction cyclic codes, and the Reed-Solomon (RS) code [5], [6] that is designed for burst errors. Other ECC schemes are proposed for multibit-error or byte-EDAC to tolerate higher soft error rate [7], [8], [9]. However, these schemes employ complex encoding or decoding algorithms, so the hardware cost and performance penalty is high.