1 Introduction
As we keep shrinking the feature size of transistors and increasing the degree of integration for integrated circuits, the capacity of semiconductor memories is getting bigger and their speed getting faster. The negative impact for larger and faster memories is that signal integrity becomes a more difficult yet important issue, so far as product quality and reliability is concerned. To enhance the signal integrity in memories, error control codes (ECCs) and error detection and correction (EDAC) schemes have been widely implemented to tolerate soft errors and enhance reliability of memory products. Extra bits containing parity check information have to be stored along with the data bits, so the hardware overhead includes the encoding/decoding circuit and the memory space for parity bits. As a matter of fact, ECC can protect the memory from attacks of both hard and soft errors. The modified Hamming code and Hsiao code [1], [2] are the most widely used single-error correctable and double-error detectable (SEC-DED) codes. For dealing with multiple errors, a code with more parity-bits is required, such as the BCH code [3], [4] that is a class of random error correction cyclic codes, and the Reed-Solomon (RS) code [5], [6] that is designed for burst errors. Other ECC schemes are proposed for multibit-error or byte-EDAC to tolerate higher soft error rate [7], [8], [9]. However, these schemes employ complex encoding or decoding algorithms, so the hardware cost and performance penalty is high.