A 12b 10MS/s Pipelined ADC Using Reference Scaling

A 12b 10MS/s pipelined ADC using reference scaling achieves 62 dB SNDR and 72 dB SFDR for a 1MHz input. The prototype IC fabricated in a 0.35mum CMOS process employs interstage amplifiers with 45dB open-loop gain and consumes 19mW from a 2.4V supply