A new structure for capacitor-mismatch-insensitive multiply-by-two amplification

A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity to capacitors' mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (times2). Comparing to the conventional multiply-by-two gain-stage, the mismatches between the capacitors has a much smaller influence on the accuracy of the gain of two (times2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35mum CMOS technology