I. Introduction
The need for high-speed low-power ADC's for software radio receivers has led to the development of a new type of time-based ADC's where the input voltage is first converted to a pulse delay time using a voltage-to-time converter (VTC), and then the pulse delay time is converted to the digital domain by a time-to-digital converter (TDC) consisting of digital logic and counter circuits [1]. This type of time based ADC can operate at very high clock and input frequencies while consuming less power and die area than other high frequency ADC architectures. Time based ADC architectures can also be made reconfigurable for use in multi-standard software radio receivers.