An Advanced Timing Characterization Method Considering Global False Path

To address the problem of accurate timing characterization, in this paper, we take the mode dependent characterization approach further and apply the notion of the global false path, the functional delay analysis between modes to a previous timing analysis of circuits and propose a new timing characterization method. Our method is applied to ISCAS-85 benchmark circuits and an industrial IP block. Experimental results show that this method is able to generate timing models with very tight path delays that are guaranteed to give correct results, and the delays of the I/O paths between the control inputs and outputs can be calculated more accurately than the previous approaches, thereby significantly improving the accuracy of timing models

1. Introduction

As the increasing complexity of integrated circuits, the accurate prediction of circuit performance is becoming an increasingly difficult problem. In a hierarchical design and verification strategy, to guarantee an accurate clock cycle of circuit modes making up a large system becomes more and more important. A timing model for each mode is to be calculated, which can then be used in place of the mode in subsequent timing analyses of the system. The timing characterization issue is addressed in this paper.