Introduction
Variation in switching delays of identical CMOS circuits in a product may occur because of systematic and random variations in MOSFET device parameters as well as in parasitic resistances and capacitances. Random variations in nominally identical circuits in close physical proximity may occur because of, for example, dopant fluctuations, line edge roughness and gate-oxide thickness variations, all of which modulate MOSFET characteristics and parasitic delay components [1]. Such variations are becoming significant with scaling of CMOS technology beyond the 130 nm node and are particularly important for circuit applications where close matching of parameters is required, such as current mirrors and SRAM memory components. Monitoring of random variations requires a statistically significant population of closely spaced test structures. Measurements on individual devices and circuits comes at the cost of increased chip real estate, test time and data analysis effort. Recently a new technique for measuring variability in MOSFET threshold voltage Vt has been described in which the Vt spread is determined from a ratio of dc currents flowing through two different configurations of an array of MOSFET's [2], [3], enabling reduced test time and data analysis effort.