A VLSI architecture for Gabor filtering in face processing applications

This paper presents a VLSI architecture for computing the Gabor jets for facial feature points from video containing faces for computer vision applications. The proposed architecture maps well onto a chain of highly pipelineable processing elements (PE) based on multiply-accumulation units with in-built ROMs. It is thus well suited for VLSI implementation, either in algorithm-specific ASIC or reconfigurable FPGA for Gabor filtering, which is one of the widespread feature extraction techniques for face processing applications such as face tracking and face recognition. Depending on the number of facial feature points (FFP) at which the Gabor jets are to be computed as well as the number of scales and orientations of the constituent Gabor filters, the number of PEs can be scaled and matched to suit the processing requirements, without sacrificing on the computational latency. Due to the regular data flow and modular structure, the linear array of PEs performing Gabor jet computations can achieve 100% hardware utilization and provide sustained throughput to match the real-time video frame rate. This VLSI architecture is mainly targeted for incorporation into a hardware implementation of dynamic face tracking system (DFTS) based on Gabor wavelets. The computation of Gabor jets is a compute-intensive task. This computational burden can be eased by adopting a VLSI hardware implementation, thereby achieving real-time performance with moderate circuit complexity.