FPGA implementation of an image segmentation algorithm using logarithmic arithmetic

Image segmentation is a process used in computer vision to automatically divide up an image. We investigate the suitability of FPGAs and Log Arithmetic for image processing. We implemented a Bayesian pixel-based segmentation algorithm in hardware, and found that certain portions of the algorithm running on a mid-range FPGA could significantly outperform an implementation running on a high-end PC.