Post layout simulation of RF CMOS integrated circuits with passive components

This paper presents a post-layout simulation methodology to verify the functionality of RF CMOS circuits before the final tape-out. The passive area of the chip, including all on-chip inductors, capacitors, and resistors, is modeled using 3D EM simulators. This method improves the accuracy of simulation results by bringing into account the effect of coupling of the passive components. Two passive test structures are examined to evaluate the improvement in the simulation results' accuracy compared with those of the individual modeling of RF passive components