The Impact of Layout on Stress-Enhanced Transistor Performance

This paper studies the sensitivity of stress-enhanced transistor performance to layout variations. Stress simulations and mobility models are calibrated and verified for test structures with SiGe source/drain as a stressor. The role of STI on the stress transfer is explored. The numerical results show that variations of 15% in drive currents and of 44% in hole mobility due to layout induced stress variations can occur in the cases studied. These deviations need to be taken into account in circuit design or to be compensated via layout modification.