On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits

Switching digital circuits produce current peaks which result in voltage fluctuations on the power supply lines due to the inductive behavior of on-chip and chip-to-package interconnects. A design technique is described in this paper to lower ground bounce in noise sensitive circuits. An on-chip noise-free ground is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor tuned in resonance with the parasitic inductance of the interconnects provide an additional low impedance ground path. Ground bounce reductions of about 68% and 22% are demonstrated for a single frequency and random noise, respectively. The noise reduction is shown to depend linearly on the physical separation between the noisy and noise sensitive blocks. The dependence of ground noise on the impedance of the low noise ground is also discussed. The proposed technique exhibits a strong tolerance to capacitance variations. The efficiency of the noise reduction technique drops by several per cent for a plusmn10% variation in the magnitude of the decoupling capacitor. The proposed technique is shown to be effective for both single frequency and random voltage fluctuations on the ground terminal