STI-induced damage and hot-carrier reliability in the narrow width short channel NMOSFET fabricated using global strained-Si technology

The width dependence of threshold voltage (V/sub t/) in the strained-Si NMOSFET relative to that of the control bulk Si device is examined. The contrasting behavior of V/sub t/, for decreasing channel width (W/sub drawn/) at a given channel length (L/sub drawn/), could be ascribed to the increased concentration of the channel dopant at the regions near the STI (shallow trench isolation)/gate edge of the strained device. Dopant enhancement is attributed to the abundance of interstitial defect sites located in both the strained-Si and the SiGe layer, due to the lattice strain arising from the STI process. Hot-carrier degradation is found to be marginally higher in the narrow-width strained device.