Component-based methodology for hardware design of a dataflow processing network

This paper proposes a new methodology for the design of reusable IP blocks used in data-flow architectures. These IP blocks are elaborated by encapsulating individual operators that constitute part of an algorithm within wrappers that possess a configurable communication layer. This IPs communicates using the VCI protocol, and the interconnections are automatically generated from a data flow graph. The interface wrapper has been designed and simulated in 0.18 /spl mu/m CMOS technology. When implemented using 2 10-bit input ports, a 12-bit output port and a FIFO depth of 8, synthesis results show that the circuit has a gate count of 1730 NAND gates with a maximum operating frequency of 400 MHz before placement and routing.

1. Introduction

Due to the increasing density and complexity of circuits, the use of component-based design methodologies is quickly gaining popularity [10]. These methodologies allow for components of a system-on-chip (SoC) to be assembled much like ICs are interconnected in a board-level design. Component-based methodology may be applied at two different levels of abstraction during the design of a complex SoC. At the first level, complex IPs are created by assembling existing components, and at the second level, the obtained IPs are composed to design the SoC. Our work is situated at the first level, where complex IPs are designed. We propose a methodology enabling automatic integration of existing components for the efficient design of hardware IPs. The key issue is the definition of generic wrappers able to interconnect a set of given components.