Developing a 3D layout for wafer fabrication plants

Wafer fabrication plants (FABs) are arranged in a two-dimension (2D) layout, usually in a single floor. These layouts imply various constraints on the work-in-process (WIP) and the material handling systems. In contrast, automated storage/retrieval systems (AS/RS) arranged in a three-dimension (3D) layout aisle, where each aisle is served by a robotic arm that moves back and forth between the aisle's entrance point and its storage locations. This paper offers an AS/RS-based 3D layout for FABs. First, we formulate the general 3D layout design problem and develop a heuristic algorithm to solve it. Then, we evaluate the proposed layout comparative to its 2D counterpart. Finally, we test the proposed layout by simulating an actual data taken from the semiconductor industry and comparing the performance of 2D and 3D layouts, 30% throughput time reduction observed