Symbolic analysis of large analog circuits using a sensitivity-driven enumeration of common spanning trees

A new approach for the generation of approximate symbolic network functions is presented. This approach is used to analyze large analog integrated circuits. It is based on a matroid intersection algorithm that directly enumerates common spanning trees of a two-graph representation of a given circuit. The approximation algorithm is based on an inspection of the sensitivity of the magnitude of a network function with respect to the different coefficients of a network function. These sensitivities as a function of frequency control the enumeration process. In this way, the algorithm enumerates a minimum number of the dominant terms for each coefficient of the network function The complete algorithm runs in O(Kmn/sup 3/) time, in which K is the average number of matroid intersections that must be generated for the approximation of each coefficient of the network function, n is the number of nodes in the linearized network and m the number of circuit elements. At the end of the paper experimental results are presented. These results indicate that this new approach is superior to other approaches to generate an approximate symbolic network function from a given two-graph.