A single-flux-quantum demultiplexer

Many applications of Single-Flux-Quantum (SFQ) circuits will rely on the transfer of multi-Gigabit per second data streams from SFQ logic to semiconductor logic for further processing. The low output voltages of superconducting circuits currently limit the data rate per channel to a few GHz. We have designed and fabricated an SFQ demultiplexer to reduce data transfer clock rates. The demultiplexer uses clocked data distribution through a binary tree architecture. The circuit was fabricated using an eight level Nb/AlO/sub x//Nb process and tested at 4.2 K.