Finite element simulation of a stress history during the manufacturing process of thin film stacks in VLSI structures

High levels of interconnection line stress are a serious reliability problem for the integrated circuit industry. These stresses, which are due to the thermal expansion coefficient difference between the line and its surroundings, as well as to nonequilibrium film growth, can lead to failure mechanisms such as voiding and cracking. Historically, stresses in these lines have typically been modeled using a fixed configuration at the final process step. The stresses are calculated as the model Is cooled to room temperature. We have developed models to calculate stresses in interconnection structures as a function of process step, such as film deposition, etching, and thermal cycles. During processing both thermal and intrinsic stresses are induced, and continuously changed by subsequent process steps. This paper presents such an analysis of simple interconnection structures which contain two-level aluminum (Al) metal layers and a tungsten (W) via connection. Stress histories of the metal and via layers are obtained and discussed. This paper also discusses the effects on interconnection stress when intrinsic stresses in various layers are taken into account.