A system for evaluating performance and cost of SIMD array designs

SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem this work addresses is the evaluation of SIMD arrays with respect to complex applications while accounting for operating frequency and chip area. The method we use is to bridge the gap between architecture-level and EDA-level modeling by using an EDA-based tool to calibrate architectural simulations. The resulting system retains much of the high throughput of the architecture-level simulator but also has accuracy similar to that of an early pass EDA synthesis and circuit simulation. We have used our system to evaluate hundreds of potential SIMD array designs with respect to real applications. Some of the results were surprising: the slowdown caused by underutilized resources was significantly more than we had anticipated.