Simulation of complete CMOS I/O circuit response to CDM stress

Enhanced compact modeling is implemented in a commercial simulator to study CMOS circuit response to charged device model (CDM) stress. Procedures for characterization of transistor snapback, oxide breakdown, and package and tester parasitics are detailed. Application to 0.25 /spl mu/m technology SRAM I/O circuits demonstrates effectiveness in analyzing CDM response and quantitatively predicting withstand levels.