Lifetime Prediction Model For Analog Devices Based On Drain Conductance Degradation Due To Hot Carrier Injection

MOSFET degradation due to hot carrier injection is the most important reliability issue in realizing submicron ultra large scaled integrated circuits. This degradation has been widely studied and lifetime simulators have also been developed for digital circuit operation [1]-[2]. On the other hand, the degradation of analog device parameters such as drain conductance due to hot carrier injection are not clearly understood and modeled. In this paper, we propose, for the first time, a physical model of analog drain conductance, gd degradation based on mobility reduction due to hot carrier generated interface states and show a reliability design guideline for analog devices.