Hot-electron injection and trapping in the gate oxide of submicron DMOS transistors

The basic parameter controlling the hot-electron safe operating area of DMOS transistors integrable in submicron bipolar-CMOS-DMOS mixed processes is the series resistance of the n-type lightly-doped layer on the source side of the devices. The hot-electron-induced degradation in DMOS transistors is correlated with the hot-electron gate current, rather than with the substrate (p-body) current, and its measurement is a sensitive, nondestructive way to bypass long-term reliability tests.