Data block processing for low power implementation of direct form FIR filters on single multiplier CMOS DSPs

In this paper, the authors propose a block processing scheme for low power implementation of FIR filters on single multiplier CMOS based digital signal processors (DSPs). The authors show that the reduction in overall power is due to a decrease in switching activity at coefficient inputs of the multiplier and both data and coefficient memory buses by a factor determined by the data input block size. Results are presented which demonstrate up to 34% savings in power. The paper presents the scheme, outlines its implementation using an example and demonstrates results with various filter orders and wordlengths.