Two-step current-memory cells with optimal dynamic range for advanced CMOS technologies

Improved two-step current-memory cell architectures employing current conveyors are proposed and compared with conventional ones over a wide range of technologies. Special emphasis is given to the evaluation of performance on very advanced state-of the art CMOS processes and the operation at low supply voltages. Up to 50% power savings can be expected with respect to conventional cells of the same performance.