A simplicial method for the simulation of transistor shorts in CMOS logic gates

CMOS logic gates in the presence of gate-to-drain or gate-to-source shorts generally depend on electrical-level simulators such as SPICE to predict the circuit behavior which is required for the purpose of fault simulation. In the light of a wide variety of unintended networks caused by transistor shorts, the use of SPICE can be very computationally intensive. In this paper, a simplified technique for characterizing the static responses of faulty CMOS gates is presented. Example circuits are used to demonstrate the feasibility of the method. The results indicate that computational time can be reduced by a factor of 10 to 100 in comparison to SPICE simulation.