Incremental compilation in the VCS environment

Viewlogic's Chronologic VCS/sup TM/ is an industry standard simulator for Verilog HDL. This paper describes incremental compilation in VCS. Incremental compilation is a general compiler optimization technique that improves turnaround time of the typical develop-test-debug-edit cycle of software development. It provides the user with the ability to make small changes to a design, while guaranteeing that the re-compilation time will be proportional to the change in the design. The compiled code simulation environment in Verilog poses unique challenges and opportunities for incremental compilation. The paper describes the issues in determining whether a design unit is unchanged since the preview compilation, or whether it needs to be re-compiled. It also addresses the specifics of incremental compilation in single-user and multiple-user environments. Finally, results are presented that demonstrate the benefits of incremental compilation in VCS.