A layout-driven yield predictor and fault generator for VLSI

The authors present an efficient approach to probability-graded fault list generation, and critical area calculation for IC yield production. The approach is also efficient to program because it is built on top of existing design rule checking routines. The accuracy of the tool is enhanced by including in the critical area calculations adjustments for defects occurring at the end of a feature and validating shorts before including the associated critical area in the sum. It would be possible to make the approach more efficient by going to an entirely graph-based approach, thus avoiding the physical tile generation step.<>