A fully pipelined programmable real-time (3/spl times/3) image filter based on capacitive threshold-logic gates

A novel programmable 2-D image filter architecture with a (3/spl times/3) window size is presented, which is based on Capacitive Threshold-Logic (CTL) gates. The filter architecture is fully pipelined, and data processing is highly parallelized in order to take advantage of the high-speed building blocks used in the design. A fixed-coefficient processing core has been designed and fabricated using conventional 1.2 micron double-polysilicon CMOS technology to evaluate the performance of the proposed architecture. The chip core area (1.8 mm/spl times/1.5 mm) compares very favorably with other image filter chips using a similar technology. Extensive post-layout simulations have shown that the chip will allow a maximum clock frequency of about 100 MHz. With this data throughput capability, the programmable image filter will be able to process high-resolution (1024/spl times/1024) pixel images at a rate of 50 frames per second.