Partial scan design based on state transition modeling

Selection of flip-flops that provide the best improvements in testability is a critical part of the partial scan design process. This paper describes a new technique for flip-flop selection that models the effect of scan in terms of the introduction of pseudo state transitions in the state transition graph. The identification of (desired) state transitions that provide for improved testability is based on an analysis of the known reachable states and desired states which ensure improved fault detection. Experiments are presented on the ISCAS 89 circuits to show significant improvements in the testability of the resulting partial scan design.