Energy recovery for low-power CMOS

Energy recovery, as a means to trade off power dissipation for performance in CMOS logic circuits, is analyzed and investigated. A mathematical model is presented to estimate the efficiency for two energy-recovery approaches under varying conditions of voltage swing, transition time, and MOS device parameters. This model can be directly compared to the well-known model for supply-voltage scaling, which is the prevalent method for trading power dissipation for performance. The two models are evaluated against SPICE simulations. Excluding body effects, which would not be present in CMOS process technologies such as Silicon-On-Insulator (SOI), the simulations and the equations agree to within 10%. The simulations also indicate that energy recovery, when implemented with circuit techniques such as bootstrapping, can significantly outperform the supply-voltage-scaled approach across a wide range of operating frequencies. To further investigate this result, two eight-bit adder designs, one based on supply-voltage scaling and the other on energy recovery, are simulated and compared.