Power consumption and performance of low-voltage bit-serial adders

By comparative simulations and chip measurements we have found that swing-restored pass transistor logic (SRPL) are suitable for low-power, low-voltage design. An enhanced SRPL full adder and a SRPL-compatible, double-edge-triggered D-type flip-flop are presented. These circuits may be simplified and jointly optimized when used in a bit-serial adder. A simulation model for finding the power consumption in bit-serial structures is discussed, and is used for comparing two bit-serial adder contestants, showing that these adders reduce the power consumption by a factor of two compared to a standard cell reference model.