Efficient area minimization for dynamic CMOS circuits

We present a new transistor ordering technique for the layout of dynamic CMOS leaf-cells which minimizes the cell area. The technique employs an Eulerian trail formulation which guarantees that the result is always of minimum width, i.e., the total diffusion area is optimum. A novel iterative improvement strategy minimizes the cell height as defined by the number of wiring tracks required to connect source and drain terminals. We were able to find a transistor ordering with the theoretical optimum area for many industrial circuits and standard test cases from the literature.