Abstract:
A novel digital architecture supporting implementation of feedforward, multilayered artificial neural networks is presented. Based on a switched bus array philosophy, par...Show MoreMetadata
Abstract:
A novel digital architecture supporting implementation of feedforward, multilayered artificial neural networks is presented. Based on a switched bus array philosophy, particular care is taken to minimize area requirements while maximizing throughput and parallelism. The architecture is well suited to support, with minimal additional changes, fault/defect tolerance with respect to faults located in the PEs (processing elements), switches, or buses.<>
Date of Conference: 29-31 January 1991
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-8186-9126-3