A 64 kB BiCMOS cache controller and memory (CCM)

The authors describe the cache controller and memory (CCM) for the external cache of a microprocessor. This CCM integrates 64 kB cache memory, TAG, and control logic using 0.7-/spl mu/m BiCMOS technology. Four-way set-associative mapping and an LRU (least recently used) replacement algorithm are adopted for the cache. The chip is 14.8/spl times/15.0 mm/sup 2/ and dissipates 3.0 W at 50 MHz. This CCM also supports copy-back protocol and bus snoop function for multiprocessor systems and has several system configuration modes for flexibility in systems. TAG and cache memory have parity bit for high reliability systems.