Architectures for pipelined Wallace tree multiplier-accumulators

A scalable architecture for pipelined and iterative Wallace tree multipliers is presented. For netlist-only multipliers, minimal latency and number of pipeline stages are achieved through a decay-driven design scheme. The architecture can be modified to a tree-of-Wallace-trees structure for regular layout, at the expense of latency. The achievable minimal cycle time equals the delay through two full adder cells, plus the setup time and delay through a register. The elemental Wallace trees in this architecture can also be used in iterative structures that provide a variety of delay/gate-count tradeoffs.<
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