Abstract:
The authors describe the architecture and design of a second-level cache chip which supports high-speed (160-Mb/s) burst transfer between multilevel caches and a newly pr...Show MoreMetadata
Abstract:
The authors describe the architecture and design of a second-level cache chip which supports high-speed (160-Mb/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. This chip includes a 32-kB data memory as well as a 42-kb tag memory and 21.7 K-gate logic, and it supports a 50-MHz CPU. Performance and design results are presented
Date of Conference: 07-09 June 1990
Date Added to IEEE Xplore: 15 October 2012
