An efficient FIR filter architecture

An efficient architecture for finite impulse response (FIR) filters is described. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR filter tap can be implemented with only 2B full adders and 2B (or 4B) latches, where B is the intermediate wordlength. Word and bit level parallelism allows high sampling rates, limited only by the full adder delay. This architecture allows the implementation of high sampling rate filters of significant length on a single field-programmable gate array (FPGA), as well implementation using more conventional VLSI techniques.<
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