Error cancellation technique for capacitor arrays in A/D and D/A converters

An error-correction technique for monolithic high-speed A/D and D/A converters, based on binary weighted capacitor arrays, is introduced. Each capacitor in the array has its individual calibration capacitor and voltage source. The calibration voltages are generated by resistive DACs. An N-bit converter requires N additional capacitors, N analog switching matrices, and N bytes of memory space. The error-acquisition technique and practical design considerations are presented.<
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