Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers were used in the process. A CMOS test chip has been designed, fabricated and tested. The test chip contained NMOS and PMOS transistors of various geometries, test structures for isolation studies, and simple circuitry. This allowed for the characterization of both the circuit performance and packing density possible with this technology. The process is described, with particular emphasis on the design and experimental results for the NMOS device. Circuit performance is presented. The results presented show that radiation detectors and CMOS electronics can be fabricated on the same substrate using a conventional CMOS process.<
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