A simple and robust niobium Josephson junction integrated circuit process

A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.