A new digital PLL for the Class I partial response channel

A digital PLL (DPLL) for using the class I partial response (PR1) channel was developed as part of a PR1-channel decoder LSI for a digital data storage III system. As a channel clock generator of this DPLL, a ring oscillator whose period can be controlled by changing its inverter number was employed. An analog-to-digital converter for sampling the readback signal was placed in the main loop of the DPLL and was driven by the reconstructed channel clock, so no master clock is needed. This DPLL can generate a channel clock of 50 MHz.